View LT6402-20_289316.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FEATURES

LT6402-20 300MHz Low Distortion, Low Noise Differential Amplifier/ADC Driver (AV = 20dB) DESCRIPTIO
The LT(R)6402-20 is a low distortion, low noise differential amplifier/ADC driver for use in applications from DC to 300MHz. The LT6402-20 has been designed for ease of use, with minimal support circuitry required. Exceptionally low input-referred noise and low distortion (with either single-ended or differential inputs) make the LT6402-20 an excellent solution for driving high speed 12-bit and 14-bit ADCs. In addition to the normal unfiltered outputs (+OUT and -OUT), the LT6402-20 has a built-in 75MHz differential low pass filter and an additional pair of filtered outputs (+OUTFILTERED, -OUTFILTERED) to reduce external filtering components when driving high speed ADCs. The output common mode voltage is easily set via the VOCM pin, eliminating an output transformer or ACcoupling capacitors in many applications. The LT6402-20 is designed to meet the demanding requirements of communications transceiver applications. It can be used as a differential ADC driver, a general-purpose differential gain block, or in other applications requiring differential drive. The LT6402-20 can be used in data acquisition systems required to function at frequencies down to DC. The LT6402-20 operates on a 5V supply and consumes 30mA. It comes in a compact 16-lead 3mm x 3mm QFN package and operates over a -40C to 85C temperature range.

300 MHz -3dB Bandwidth Fixed Gain of 20dB Low Distortion: 48.5dBm OIP3, -81dBc HD3 (20MHz, 2VP-P) Low Noise: 12.4dB NF, en = 1.9nV/Hz (20MHz) Differential Inputs and Outputs Additional Filtered Outputs Adjustable Output Common Mode Voltage DC- or AC-Coupled Operation Minimal Support Circuitry Required Small 0.75mm Profile 16-Lead 3mm x 3mm QFN Package
APPLICATIO S

Differential ADC Driver for: Imaging Communications Differential Driver/Receiver Single Ended to Differential Conversion Differential to Single Ended Conversion Level Shifting IF Sampling Receivers SAW Filter Interfacing/Buffering
, LTC and LT are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
Distortion vs Frequency, Differential Input, No RLOAD
-10 UNFILTERED OUTPUTS VOUT = 2VP-P -30 DISTORTION (dBc) -50 -70 HD2 -90
0.1F -INB -INA 0.1F VOCM +OUT LT6402-20 -OUT IN +INB +INA
6402 TA01a
10 10
VCM AIN+ LTC2249 AIN-
-110 -130 1 10 FREQUENCY (MHz) 100
64022 G04
U
U
U
HD3
640220f
1
LT6402-20 ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW +INA +INB -INA -INB
Total Supply Voltage (VCCA/VCCB/VCCC to VEEA/VEEB/VEEC) ...................................................5.5V Input Current (+INA, -INA, +INB, -INB, VOCM, ENABLE)................................................10mA Output Current (Continuous) +OUT, -OUT ...................................................100mA +OUTFILTERED, -OUTFILTERED......................30mA Output Short Circuit Duration (Note 2) ............ Indefinite Operating Temperature Range (Note 3) ... -40C to 85C Specified Temperature Range (Note 4) .... -40C to 85C Storage Temperature Range................... -65C to 125C Junction Temperature ........................................... 125C Lead Temperature Range (Soldering 10 sec) ........ 300C
16 15 14 13 VCCC 1 VOCM 2 VCCA 3 VEEA 4 5 +OUT 6 +OUTFILTERED 7 -OUTFILTERED 8 -OUT 17 12 VEEC 11 ENABLE 10 VCCB 9 VEEB
UD PACKAGE 16-LEAD (3mm x 3mm) PLASTIC QFN TJMAX = 125C, JA = 68C/W, JC = 4.2C/W EXPOSED PAD IS VEE (PIN 17) MUST BE SOLDERED TO THE PCB
ORDER PART NUMBER LT6402CUD-20 LT6402IUD-20
UD PART MARKING* LCBC LCBC
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
DC ELECTRICAL CHARACTERISTICS
SYMBOL GDIFF VSWINGMIN VSWINGMAX VSWINGDIFF IOUT VOS TCVOS Output Voltage Swing Output Current Drive Input Offset Voltage PARAMETER Gain CONDITIONS
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA shorted to +INB (+IN), -INA shorted to -INB (-IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
MIN
TYP 20 0.25
MAX 20.9 0.35 0.5
UNITS dB V V V V VP-P VP-P mA
Input/Output Characteristics (+INA, +INB, -INA, -INB, +OUT, -OUT, +OUTFILTERED, -OUTFILTERED) Differential (+OUT, -OUT), VIN = 160mV Differential Single-Ended +OUT, -OUT, +OUTFILTERED, -OUTFILTERED, VIN = 600mV Differential Single-Ended +OUT, -OUT, +OUTFILTERED, -OUTFILTERED, VIN = 600mV Differential Differential (+OUT, -OUT), VIN = 600mV Differential 18.9

3.4 3.3 6.1 5.6 30 -6.5 -10
3.6 7 35 1 2.5 6.5 10
Input Offset Voltage Drift
TMIN to TMAX
V/C
640220f
2
U
mV mV
W
U
U
WW
W
LT6402-20 DC ELECTRICAL CHARACTERISTICS
SYMBOL IVRMIN IVRMAX RINDIFF CINDIFF CMRR ROUTDIFF COUTDIFF GCM VOCMMIN VOCMMAX VOSCM IBIASCM RINCM CINCM ENABLE Pin VIL VIH IIL IIH Power Supply VS IS ISDISABLED PSRR Operating Range Supply Current Supply Current (Disabled) Power Supply Rejection Ratio ENABLE = 0.8V ENABLE = 2V 4V to 5.5V

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA shorted to +INB (+IN), -INA shorted to -INB (-IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
PARAMETER Input Voltage Range, MIN Input Voltage Range, MAX Input Resistance Input Capacitance Common Mode Rejection Ratio Output Resistance Output Capacitance Common Mode Gain Output Common Mode Voltage Adjustment Range, MIN Output Common Mode Voltage Adjustment Range, MAX Output Common Mode Offset Voltage VOCM Input Bias Current VOCM Input Resistance VOCM Input Capacitance ENABLE Input Low Voltage ENABLE Input High Voltage ENABLE Input Low Current ENABLE Input High Current ENABLE = 0.8V ENABLE = 2V

CONDITIONS Single-Ended Single-Ended

MIN 3.9 77 45
TYP
MAX 0.9
UNITS V V pF dB pF
100 1 70 0.3 0.8
122
Input Common Mode 0.9V to 3.9V
Common Mode Voltage Control (VOCM Pin) Differential (+OUT, -OUT), VOCM = 1.2V to 3.6V Differential (+OUT, -OUT), VOCM = 1.4V to 3.4V

0.9 0.9
1
1.1 1.1 1.2 1.4
V/V V/V V V V V
Single-Ended
3.6 3.4 -30 4 5 0.8 3 1 0.8 2 0.5 1 4 24 55 5 30 250 90 3 5.5 37 500 30 15
Measured from VOCM to Average of +OUT and -OUT

mV A M pF V V A A V mA A dB
640220f
3
LT6402-20 AC ELECTRICAL CHARACTERISTICS
SYMBOL -3dBBW 0.1dBBW 0.5dBBW SR ts1% tON tOFF -3dBBWCM SRCM 10MHz Signal Second/Third Harmonic Distortion Third-Order IMD OIP310M NF en10M 20MHz Signal Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential (+OUTFILTERED, -OUTFILTERED) 2VP-P Differential (+OUT, -OUT) 2VP-P Differential Composite (+OUTFILTERED, -OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz 2VP-P Differential Composite (+OUT, -OUT), RL = 400, f1 = 19.5MHz, f2 = 20.5MHz OIP320M NF en20M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100 Differential (+OUTFILTERED, -OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz Measured Using DC954A Demo Board -81 -81 -91 -91 48.5 12.37 1.9 18 dBc dBc dBc dBc dBm dB nV/Hz dBm Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100 2VP-P Differential (+OUTFILTERED, -OUTFILTERED) 2VP-P Differential (+OUT, -OUT) 2VP-P Differential Composite (+OUTFILTERED, -OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz Differential (+OUTFILTERED, -OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz Measured Using DC954A Demo Board -96 -96 -88.3 47 12.31 1.85 19.5 dBc dBc dBc dBm dB nV/Hz dBm PARAMETER -3dB Bandwidth Bandwidth for 0.1dB Flatness Bandwidth for 0.5dB Flatness Slew Rate 1% Settling Turn-On Time Turn-Off Time Common Mode Small-Signal -3dB Bandwidth Common Mode Slew Rate 0.1VP-P at VOCM, Measured Single-Ended at +OUT and -OUT 1.3V to 3.4V Step at VOCM Input/Output Characteristics 200mVP-P Differential (+OUT, -OUT) 200mVP-P Differential (+OUT, -OUT) 200mVP-P Differential (+OUT, -OUT) 3.2VP-P Differential (+OUT, -OUT) 1% Settling for a 1VP-P at VOCM Differential Step (+OUT, -OUT) 200 300 30 80 1000 8 40 250 300 135 MHz MHz MHz V/s ns ns ns MHz V/s
TA = 25C, VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA shorted to +INB (+IN), -INA shorted to -INB (-IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
CONDITIONS MIN TYP MAX UNITS
Common Mode Voltage Control (VOCM Pin)
Noise/Harmonic Performance Input/Output Characteristics
640220f
4
LT6402-20 AC ELECTRICAL CHARACTERISTICS
SYMBOL 25MHz Signal Second/Third Harmonic Distortion Third-Order IMD 2VP-P Differential (+OUTFILTERED, -OUTFILTERED) 2VP-P Differential (+OUT, -OUT) 2VP-P Differential Composite (+OUTFILTERED, -OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz 2VP-P Differential Composite (+OUT, -OUT), RL = 100, f1 = 24.5MHz, f2 = 25.5MHz OIP325M NF en25M Output Third-Order Intercept Noise Figure Input Referred Noise Voltage Density 1dB Compression Point RL = 100 Differential (+OUTFILTERED, -OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz Measured Using DC954A Demo Board -75 -70 -90 -87 48 12.46 1.9 16.6 dBc dBc dBc dBc dBm dB nV/Hz dBm PARAMETER
TA = 25C, VCCA = VCCB = VCCC = 5V,VEEA = VEEB = VEEC = 0V, ENABLE = 0.8V, +INA shorted to +INB (+IN), -INA shorted to -INB (-IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
CONDITIONS MIN TYP MAX UNITS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: As long as output current and junction temperature are kept below the Absolute Maximum Ratings, no damage to the part will occur.
Note 3: The LT6402 is guaranteed functional over the operating temperature range of -40C to 85C. Note 4: The LT6402C is guaranteed to meet specified performance from 0C to 70C. It is designed, characterized and expected to meet specified performance from -40C and 85C but is not tested or QA sampled at these temperatures. The LT6402I is guaranteed to meet specified performance from -40C to 85C.
640220f
5
LT6402-20 TYPICAL PERFOR A CE CHARACTERISTICS
Frequency Response RLOAD = 400
25 UNFILTERED OUTPUTS 20 THIRD ORDER IMD (dBc) FILTERED OUTPUTS 15 GAIN (dB) 10 5 VIN = 200mVP-P 0 UNFILTERED: RLOAD = 400 FILTERED: RLOAD = -5 300 (EXTERNAL) + 100 (INTERNAL, FILTERED OUTPUTS) -10 10 1 100 FREQUENCY (MHz) -60 -65 -70 -75 -80 -85 -90 FILTERED OUTPUTS -95 1000
64022 G01
DISTORTION (dBc)
Distortion vs Frequency, Differential Input, No RLOAD
-10 -30 NOISE FIGURE (dB) DISTORTION (dBc) -50 -70 HD2 -90 UNFILTERED OUTPUTS VOUT = 2VP-P 30 25 20 15 10 5 0 1 10 FREQUENCY (MHz) 100
64022 G04
INPUT REFERRED NOISE VOLTAGE (nV/Hz)
HD3
-110 -130
6
UW
Third Order Intermodulation Distortion vs Frequency Differential Input, No RLOAD
2 TONES, 2VP-P COMPOSITE 1MHz TONE SPACING -10 -30 -50
Distortion vs Frequency Differential Input, No RLOAD
FILTERED OUTPUTS VOUT = 2VP-P
HD3 -70 HD2 -90
UNFILTERED OUTPUTS
-110 -130 1 10 FREQUENCY (MHz) 100
64022 G03
5
10
15 20 25 FREQUENCY (MHz)
30
35
64022 G02
Noise Figure vs Frequency
8 7 6 5 4 3 2 1 0
Input Referred Noise Voltage vs Frequency
MEASURED USING DC954A DEMO BOARD 10 100 FREQUENCY (MHz) 1000
64022 G05
10
100 FREQUENCY (MHz)
1000
64022 G06
640220f
LT6402-20 TYPICAL PERFOR A CE CHARACTERISTICS
Differential Input Impedance vs Frequency
INPUT IMPEDANCE (MAGNITUDE , PHASE) 400 350 OUTPUT IMPEDANCE () 300 250 200 150 100 50 0 -50 -100 1 10 100 FREQUENCY (MHz) 1000
64022 G07
OUTPUT VOLTAGE (V)
IMPEDANCE MAGNITUDE
IMPEDANCE PHASE 0 10 100 FREQUENCY (MHz) 1000
64022 G08
Turn-On Time
4 3 2 AMPLITUDE (dBFS) VOLTAGE (V) 1 6 4 2 ENABLE 0 -2 0 250 500 750 TIME (ns) 1000 1250 -OUT +OUT 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
AMPLITUDE (dBFS)
UW
64022 G10
Differential Output Impedance vs Frequency
1000 UNFILTERED OUTPUTS 2.325 2.300 2.275 100 2.250 2.225 2.200 2.175 2.150 2.125 2.100 2.075
Small-Signal Transient Response
RLOAD = 100 PER OUTPUT
10
1
0
5
10 15 20 25 30 35 40 45 50 TIME (ns)
64022 G09
10MHz 8192 Point FFT, Filtered Outputs LT6402-20 Driving LTC2249 14-Bit ADC
8192 POINT FFT fIN = 10MHz, -1dBFS FILTERED OUTPUTS
25MHz 8192 Point FFT, Filtered Outputs LT6402-20 Driving LTC2249 14-Bit ADC
0 8192 POINT FFT -10 fIN = 25MHz, -1dBFS -20 FILTERED OUTPUTS -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
0
5
10
15 20 25 30 FREQUENCY (MHz)
35
40
64022 G11
64022 G12
640220f
7
LT6402-20 PI FU CTIO S
VOCM (Pin 2): This pin sets the output common mode voltage. Without additional biasing, both inputs bias to this voltage as well. This input is high impedance. VCCA, VCCB, VCCC (Pins 3, 10, 1): Positive Power Supply (Normally Tied to 5V). All three pins must be tied to the same voltage. Bypass each pin with 1000pF and 0.1F capacitors as close to the package as possible. Split supplies are possible as long as the voltage between VCC and VEE is 5V. VEEA, VEEB, VEEC (Pins 4, 9, 12): Negative Power Supply (Normally Tied to Ground). All three pins must be tied to the same voltage. Split supplies are possible as long as the voltage between VCC and VEE is 5V. If these pins are not tied to ground, bypass each pin with 1000pF and 0.1F capacitors as close to the package as possible. +OUT, -OUT (Pins 5, 8): Outputs (Unfiltered). These pins are high bandwidth, low-impedance outputs. The DC output voltage at these pins is set to the voltage applied at VOCM. +OUTFILTERED, -OUTFILTERED (Pins 6, 7): Filtered Outputs. These pins add a series 50 resistor from the unfiltered outputs and three 14pF capacitors. Each output has 14pF to VEE, plus an additional 14pF between each pin (See the Block Diagram). This filter has a -3dB bandwidth of 75MHz. ENABLE (Pin 11): This pin is a TTL logic input referenced to the VEEC pin. If low, the LT6402 is enabled and draws typically 30mA of supply current. If high, the LT6402 is disabled and draws typically 250A. +INA, +INB (Pins 15, 16): Positive Inputs. These pins are normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. -INA, -INB (Pins 14, 13): Negative Inputs. These pins are normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias to the voltage applied to the VOCM pin. Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split supplies are used, DO NOT tie the pad to ground.
8
U
U
U
640220f
LT6402-20 BLOCK DIAGRA W
500 -INA 14 -INB 13 100 VCCA VEEA 14pF +OUT A 5 +OUTFILTERED VEEA 500 VCCC 50 6 VOCM 100
- +
+
C 14pF
2
-
500 +INA 16 +INB 15 100 VCCB VEEC 50 100 -OUTFILTERED 7 -OUT B 8 14pF VEEB 500
+ -
VEEB
BIAS
3 VCCA
10 VCCB
1 VCCC
11 ENABLE
4 VEEA
9 VEEB
12 VEEC
6402 BD
640220f
9
LT6402-20 APPLICATIO S I FOR ATIO
Circuit Description The LT6402 is a low noise, low distortion differential amplifier/ADC driver with: * -3dB bandwidth DC to 300MHz * Fixed gain independent of RLOAD 10V/V (20dB) * Differential input impedance 100 * Low output impedance * Built-in, user adjustable output filtering * Requires minimal support circuitry Referring to the block diagram, the LT6402-20 uses a closed-loop topology which incorporates 3 internal amplifiers. Two of the amplifiers (A and B) are identical and drive the differential outputs. The third amplifier is used to set the output common mode voltage. Gain and input impedance are set by the 500 and 100 resistors in the internal feedback network. Output impedance is low, determined by the inherent output impedance of amplifiers A and B, and further reduced by internal feedback. The LT6402-20 also includes built-in single-pole output filtering. The user has the choice of using the unfiltered outputs, the filtered outputs (75MHz -3dB lowpass), or modifying the filtered outputs to alter frequency response by adding additional components. Many lowpass and bandpass filters are easily implemented with just one or two additional components. The LT6402-20 has been designed to minimize the need for external support components such as transformers or AC-coupling capacitors. As and ADC driver, the LT6402-20 requires no external components except for power-supply bypass capacitors. This allows DC-coupled operation for applications that have frequency ranges including DC. At
10
U
the outputs, the common mode voltage is set via the VOCM pin, allowing the LT6402-20 to drive ADCs directly. No output AC-coupling capacitors or transformers are needed. At the inputs, signals can be differential or single-ended with virtually no difference in performance. Furthermore, DC levels at the inputs can be set independently of the output common mode voltage. These input characteristics often eliminate the need for an input transformer and/or AC-coupling capacitors. Input Impedance and Matching Networks Calculation of the input impedance of the LT6402-20 is not straightforward from examination of the block diagram because of the internal feedback network. In addition, the input impedance when driven differentially is different than when driven single-ended.
Differential LT6402-20 100 Single-Ended 85.9
W
U
U
For single-ended 50 applications, a 121 shunt matching resistor to ground will result in the proper input termination (Figure 1). For differential inputs there are several termination options. If the input source is 50 differential, then the input matching can be accomplished by either a 100 shunt resistor across the inputs (Figure 3), or equivalent 49.9 shunt resistors on each of the inputs to ground (Figure 2). If additional AC gain is desired, an impedance ratio transformer can also be used to better match impedances.
13 14 0.1F LT6402-20 IF IN 121 ZIN = 50 SINGLE-ENDED 15 16 +INB +INA +OUT
-INB -INA
-OUT
8
5
6402 F01
Figure 1. Input Termination for Single-Ended 50 Input Impedance
640220f
LT6402-20 APPLICATIO S I FOR ATIO
Single-Ended to Differential Operation The LT6402-20's performance with single-ended inputs is comparable to its performance with differential inputs. This excellent single-ended performance is largely due to the internal topology of the LT6402-20. Referring to the block diagram, if the +INA and +INB pins are driven with a single-ended signal (while -INA and -INB are tied to AC ground), then the +OUT and -OUT pins are driven differentially without any voltage swing needed from amplifier C. Single-ended to differential conversion using more conventional topologies suffers from performance limitations due to the common mode amplifier. Driving ADCs The LT6402-20 has been specifically designed to interface directly with high speed Analog to Digital Converters (ADCs). In general, these ADCs have differential inputs, with an input impedance of 1k or higher. In addition, there is generally some form of lowpass or bandpass filtering just prior to the ADC to limit input noise at the ADC, thereby improving system signal to noise ratio. Both the unfiltered
13 IF IN- 49.9 ZIN = 50 DIFFERENTIAL 15 IF IN+ 49.9 16 +INB +INA 14
Figure 2. Input Termination for Differential 50 Input Impedance
13 IF IN- ZIN = 50 DIFFERENTIAL IF IN+ 14
-INB -INA -OUT LT6402-20
8
100 15 16 +INB +INA
+OUT
5
6402 F03
Figure 3. Alternate Input Termination for Differential 50 Input Impedance
U
and filtered outputs of the LT6402-20 can easily drive the high impedance inputs of these differential ADCs. If the filtered outputs are used, then cutoff frequency and the type of filter can be tailored for the specific application if needed. Wideband Applications (Using the +OUT and -OUT Pins) In applications where the full bandwidth of the LT6402-20 is desired, the unfiltered output pins (+OUT and -OUT) should be used. They have a low output impedance; therefore, gain is unaffected by output load. Capacitance in excess of 5pF placed directly on the unfiltered outputs results in additional peaking and reduced performance. When driving an ADC directly, a small series resistance is recommended between the LT6402-20's outputs and the ADC inputs (Figure 4). This resistance helps eliminate any resonances associated with bond wire inductances of either the ADC inputs or the LT6402-20's outputs. A value between 10 and 25 gives excellent results.
-INB -INA -OUT LT6402-20 +OUT 8 5
6402 F02
W
U
U
-OUT LT6402-20
8
10 TO 25
ADC 10 TO 25
+OUT
5
6402 F04
Figure 4. Adding Small Series R at LT6402 Output
640220f
11
LT6402-20 APPLICATIO S I FOR ATIO
Filtered Applications (Using the +OUTFILTERED and -OUTFILTERED Pins) Filtering at the output of the LT6402-20 is often desired to provide either anti-aliasing or improved signal to noise ratio. To simplify this filtering, the LT6402-20 includes an additional pair of differential outputs (+OUTFILTERED and -OUTFILTERED) which incorporate an internal lowpass filter network with a -3dB bandwidth of 75MHz (Figure 5). These pins each have an output impedance of 50. Internal capacitances are 14pF to VEE on each filtered output, plus an additional 14pF capacitor connected differentially between the two filtered outputs. This resistor/capacitor combination creates filtered outputs that look like a series 50 resistor with a 42pF capacitor shunting each filtered output to AC ground, giving a -3dB bandwidth of 75MHz. The filter cutoff frequency is easily modified with just a few external components. To increase the cutoff frequency, simply add 2 equal value resistors, one between +OUT and +OUTFILTERED and the other between -OUT and -OUTFILLT6402-20 VEE 50 14pF 7 -OUTFILTERED 14pF 50 6 +OUTFILTERED 14pF VEE 5 +OUT
6402 F05
8 -OUT 14pF 50 FILTERED OUTPUT (75MHz)
Figure 5. LT6402-20 Internal Filter Topology -3dB BW 75MHz
LT6402-20 LT6402-20 VEE 50 14pF 50 7 -OUTFILTERED 14pF 50 6 +OUTFILTERED 14pF VEE 5 +OUT
6402 F06
8 -OUT 50
FILTERED OUTPUT (150MHz) 50
50
Figure 6. LT6402-20 Internal Filter Topology Modified for 2x Filter Bandwidth (2 External Resistors)
12
U
TERED (Figure 6). These resistors are in parallel with the internal 50 resistor, lowering the overall resistance and increasing filter bandwidth. To double the filter bandwidth, for example, add two external 50 resistors to lower the series resistance to 25. The 42pF of capacitance remains unchanged, so filter bandwidth doubles. To decrease filter bandwidth, add two external capacitors, one from +OUTFILTERED to ground, and the other from -OUTFILTERED to ground. A single differential capacitor connected between +OUTFILTERED and -OUTFILTERED can also be used, but since it is being driven differentially it will appear at each filtered output as a single-ended capacitance of twice the value. To halve the filter bandwidth, for example, two 42pF capacitors could be added (one from each filtered output to ground). Alternatively one 21pF capacitor could be added between the filtered outputs, again halving the filter bandwidth. Combinations of capacitors could be used as well; a three capacitor
LT6402-20 VEE 50 14pF 7 -OUTFILTERED 14pF FILTERED OUTPUT (37.5MHz) 8 -OUT 14pF 6 +OUTFILTERED 14pF VEE 5 +OUT
6402 F07
W
U
U
14pF
Figure 7. LT6402-20 Internal Filter Topology Modified for 1/2x Filter Bandwidth (3 External Capacitors)
VEE 14pF
8 -OUT
7 -OUTFILTERED
14pF
FILTERED OUTPUT
6 +OUTFILTERED 14pF VEE 5 +OUT
6402 F08
Figure 8. LT6402-20 Output Filter Modified for Bandpass Filtering (1 External Inductor, 1 External Capacitor)
640220f
LT6402-20 APPLICATIO S I FOR ATIO
solution of 14pF from each filtered output to ground plus a 14pF capacitor between the filtered outputs would also halve the filter bandwidth (Figure 7). Bandpass filtering is also easily implemented with just a few external components. An additional 560pF and 62nH, each added differentially between +OUTFILTERED and -OUTFILTERED creates a bandpass filter with a 26MHz center frequency, -3dB points of 23MHz and 30MHz, and 1.6dB of insertion loss (Figure 8). Output Common Mode Adjustment The LT6402-20's output common mode voltage is set by the VOCM pin. It is a high-impedance input, capable of setting the output common mode voltage anywhere in a range from 1.1V to 3.6V. Bandwidth of the VOCM pin is typically 300MHz, so for applications where the VOCM pin is tied to a DC bias voltage, a 0.1F capacitor at this pin is recommended. For best distortion performance, the voltage at the VOCM pin should be between 1.8V and 2.6V. When interfacing with most ADCs, there is generally a VOCM output pin that is at about half of the supply voltage of the ADC. For 5V ADCs such as the LTC17XX family, this VOCM output pin should be connected directly (with the addition of a 0.1F capacitor) to the input VOCM pin of the LT6402-20. For 3V ADCs such as the LTC22XX families, the LT6402-20 will function properly using the 1.65V from the ADC's VCM reference pin, but improved Spurious Free Dynamic Range (SFDR) and distortion performance can be achieved by level-shifting the LTC22XX's VCM reference voltage up to at least 1.8V. This can be accomplished as shown in Figure 9 by using a resistor divider between the LTC22XX's VCM output pin and VCC and then bypassing the LT6402-20's VOCM pin with a 0.1F capacitor. For a common mode voltage above 1.9V, AC coupling capacitors are recommended between the LT6402-20 and LTC22XX ADCs because of the input voltage range constraints of the ADC. Large Output Voltage Swings The LT6402-20 has been designed to provide the 3.2VPP output swing needed by the LTC1748 family of 14-bit low-noise ADCs. This additional output swing improves system SNR by up to 4dB.
U
Input Bias Voltage and Bias Current The input pins of the LT6402-20 are internally biased to the voltage applied to the VOCM pin. No external biasing resistors are needed, even for AC-coupled operation. The input bias current is determined by the voltage difference between the input common mode voltage and the VOCM pin (which sets the output common mode voltage). For example, if the inputs are tied to 2.5V with the VOCM pin at 2.2V, then a total input bias current of 1mA will flow into the LT6402-20's +INA and +INB pins. Furthermore, an additional input bias current totaling 1mA will flow into the -INA and -INB inputs. Application (Demo) Boards The DC954A Demo Board has been created for stand-alone evaluation of the LT6402-20 with either single-ended or differential input and output signals. As shown, it accepts a single-ended input and produces a single-ended output so that the LT6402-20 can be evaluated using standard laboratory test equipment. For more information on this Demo Board, please refer to the Demo Board section of this data sheet. There are also additional demo boards available that combine the LT6402-20 with a variety of different Linear Technology ADCs. Please contact the factory for more information on these demo boards.
3V 11k 1.9V 0.1F 13 14 0.1F 15 IF IN 121 16 -INB -INA 2 VOCM +OUTFILTERED LT6402-20 -OUTFILTERED +INB +INA
6402 F9
W
U
U
4.02k 31 1.5V
6
10 10
1
VCM AIN+ LTC22xx AIN-
7
2
Figure 9. Level Shifting 3V ADC VCM Voltage for Improved SFDR
640220f
13
LT6402-20 TYPICAL APPLICATIO U
LT6402
640220f
14
LT6402-20 PACKAGE DESCRIPTIO U
UD Package 16-Lead Plastic QFN (3mm x 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 0.75 0.05 BOTTOM VIEW--EXPOSED PAD R = 0.115 TYP 15 16 0.40 0.10 1 1.45 0.10 (4-SIDES) 2 PIN 1 NOTCH R = 0.20 TYP OR 0.25 x 45 CHAMFER
(UD16) QFN 0904
3.50 0.05 1.45 0.05 2.10 0.05 (4 SIDES)
3.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6)
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
640220f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6402-20 TYPICAL APPLICATIO
R18 0 GND TP1 ENABLE 1 R2 0 R4 49.90 C2 0.1F 1 T1 5 1:1 Z-RATIO 1 2 1 J2 +IN 0dB 4 M/A-COM ETC1-1T 3 C1 0.1F 1 R1 [1] R3 49.90 2 VCC C10 2 0.01F 1 R5 0 2 2 14 0dB 15 +INB 12 R6 0 13 VEEC -INB 11 ENABLE 10 9 -OUT R10 8 24.9 R8 [1] R7 [1] R9 24.9 L1 [1] 2 1 C4 0.1F 1 2 T2 3 4:1 Z-RATIO 4 C8 [1] C3 0.1F 1 2 1 2 C13 0.01F C16 [1] 2 1 C22 0.1F R13 [1] 1 2 C11 [1] R14 0 1 SW1 2
J1 -IN
C21 0.1F
*
+OUTFILTERED
6
1 R11 75
MINI5 +8dB CIRCUITS TCM 4-19
*
VCC R19 14k J3 VOCM R20 11k
J6 TEST IN
5
T3 1:4
1 2
C19, 0.1F 1 2 R21 [1] C6 0.1F 1 2
*
1
2
4 MINICIRCUITS TCM 4-19 TP2 VCC 1 2 1 C14 4.7F VCC
3
1
MINI5 CIRCUITS TCM 4-19
2 1
C15 1F
NOTES: UNLESS OTHERWISE SPECIFIED, [1] DO NOT STUFF.
TP3 GND 1
*
RELATED PARTS
PART NUMBER LT1993-2 LT1993-4 LT1993-10 LT5514 LT6600-5 LT6600-10 LT6600-20 DESCRIPTION 800MHz Differential Amplifier/ADC Driver 900MHz Differential Amplifier/ADC Driver 700MHz Differential Amplifier/ADC Driver Ultralow Distortion IF Amplifier/ADC Driver Very Low Noise Differential Amplifier and 5MHz Lowpass Filter Very Low Noise Differential Amplifier and 10MHz Lowpass Filter Very Low Noise Differential Amplifier and 20MHz Lowpass Filter COMMENTS AV = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz AV = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz AV = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz Digitally Controlled Gain Output IP3 47dBm at 100MHz 82dB S/N with 3V Supply, SO-8 Package 82dB S/N with 3V Supply, SO-8 Package 76dB S/N with 3V Supply, SO-8 Package
16 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006
U
Demo Circuit DC954A Schematic (AC Test Circuit)
R17 0 VCC VCC 3 2 R16 0 1 C17 1000pF 2 1 C18 0.01F VCC VCCB VEEB R12 75 -INA -OUTFILTERED LT6402-20 7 J4 -OUT +18.8dB R15 [1] +14dB 2 J5 +OUT 16 +INA VCCC 1 VOCM 2 VCCA 3 +OUT VEEA 4 5 VCC 2 1 C9 2 1000pF 1 2 1 C12 1000pF 2 1 C7 0.01F C5 0.1F 1 2 R22 [1] C20, 0.1F 2 3 T4 4:1 4 J7 TEST OUT
6402 TA02
* *
* *
640220f LT 0106 * PRINTED IN USA

▲Up To Search▲

Price & Availability of LT6402-20

	To Download LT6402-20 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .